The present invention relates to an analog frequency divider circuit which is operable stably to a high frequency in the gigahertz (GHz) band, and further relates to a frequency synthesizer using a frequency divider circuit.
Conventionally, a digital frequency divider circuit employing a flip-flop (abbreviated as F/F) has been widely used as a frequency divider indispensable for the PLL (phase-locked loop) which is used to stabilize the local oscillator source in automobile telephones and various radio equipments. In this digital frequency divider circuit, for example, a synchronous type masterslave F/F is used. However, the digital frequency divider circuit of such a configuration is composed of numerous transistors and diodes, and thus the circuit structure is complicated. Furthermore, since the maximum operating frequency is about 1 GHz in the case where Si is used, and about several GHz where GaAs is used, difficulties not only arise in manufacturing the frequency divider circuit when it is desired to operate in a range extending to a higher frequency, but power consumption increases to a great extent. These are disadvantageous in this type of frequency divider circuit. For this reason, with increasing requirements for higher utilizable frequencies and for lower power consumption, analog frequency divider circuits also have been utilized.
As an analog frequency divider circuit for high frequencies, a so-called feedback frequency divider circuit is used in which, where f.sub.1 is an input frequency, f.sub.2 is a frequency-divided output frequency, and n is the frequency-dividing ratio, the input frequency f.sub.1 and the (n-1)th higher harmonic of the output frequency f.sub.2 are applied to a modulator and the difference frequency therebetween is outputted. In this type of analog frequency divider circuit, there are drawbacks in that since the harmonic oscillator is always oscillating, an undesired wave is possibly outputted even when there is no input signal, and further the operating frequency band is also narrow.
Furthermore, in a conventional frequency synthesizer using the frequency divider circuit there is a drawback in that, as the oscillation frequency becomes high, the frequency divider circuit in the prescaler is required to be operated at high speeds, electric power consumption increases, and the operating margin is lost resulting in poor stability. Therefore power consumption of the synthesizer remarkably increases, and unstable operation cannot be avoided.